Project ForgeComputer Organization & Architecture
Memory Hierarchy & Floating Point
GATE 2024
Medium
Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?
- A2,56,000
- B3,200
- 25,60,000
- D32,000
Explanation
Cycles used for DMA per second = 1% × 4×10^6 = 40,000 cycles/sec. Each cycle transfers 8 bytes, so bytes/sec = 40,000×8 = 320,000 bytes/sec = 320,000×8 bits/sec = 25,60,000 bits/sec.
Source: GATE CS 2024 Session 2 (CS2) (2024)
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