Project ForgeComputer Organization & Architecture
Pipelining & Instruction Sets
GATE 2023
Medium
Consider a 3-stage pipelined processor having a delay of 10 ns, 20 ns, and 14 ns, for the first, second, and third stages, respectively. Assume that there is no other delay and the processor does not suffer from any pipeline hazards. Also assume that one instruction is fetched every cycle. The total execution time for executing 100 instructions on this processor is ____ ns.
2040 ns
Explanation
The pipeline's clock cycle time is set by the slowest stage: max(10,20,14)=20 ns. Total time for n instructions through a k-stage pipeline = (n+k−1) cycles = (100+3−1)×20 = 102×20 = 2040 ns.
Source: GATE CS 2023 (2023)
This question is part of a 15-day revision cycle — sign in and Project Forge will bring it back the day before you'd forget it.