Project ForgeConsider the following statements.
I. Daisy chaining is used to assign priorities in attending interrupts. II. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt. III. In polling, the CPU periodically checks the status bits to know if any device needs its attention. IV. During DMA, both the CPU and DMA controller can be bus masters at the same time.
Which of the above statements is/are TRUE?
- AI and II only
- BI and IV only
- I and III only
- DIII only
Explanation
I is TRUE: daisy chaining is a classic hardware priority-assignment scheme for interrupts. II is FALSE: a VECTORED interrupt means the device itself supplies its identifying vector, so the CPU does NOT need to poll — polling is used for non-vectored interrupts instead. III is TRUE: this is exactly the definition of polling. IV is FALSE: only one device can be bus master at any given time; DMA controller becomes bus master only after the CPU releases the bus. So I and III only.
Source: GATE CS 2020 (2020)
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