Project ForgeConsider the following data path diagram with registers MAR, MDR, IR, PC, R0-R7, TEMP1, TEMP2, and an ALU, all connected via a common BUS. Consider an instruction: R0 ← R1 + R2. The following steps are used to execute it over the given data path (PC is incremented appropriately; subscripts r/w indicate read/write):
1. R2ᵣ, TEMP1ᵣ, ALUadd, TEMP2w 2. R1ᵣ, TEMP1w 3. PCᵣ, MARw, MEMᵣ 4. TEMP2ᵣ, R0w 5. MDRᵣ, IRw
Which one of the following is the correct order of execution of the above steps?
- A2, 1, 4, 5, 3
- B1, 2, 4, 3, 5
- 3, 5, 2, 1, 4
- D3, 5, 1, 2, 4
Explanation
Instruction execution must fetch before it can decode/execute. Fetch: step 3 (PC→MAR, then read memory into MDR) must happen first, followed by step 5 (MDR→IR, loading the fetched instruction). Then execute R0←R1+R2: step 2 moves R1 into TEMP1, step 1 adds R2 to TEMP1 and stores the sum in TEMP2, and finally step 4 moves TEMP2 into R0. Order: 3, 5, 2, 1, 4.
Source: GATE CS 2020 (2020)
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