Project ForgeConsider a paging system that uses a 1-level page table residing in main memory and a TLB for address translation. Each main memory access takes 100 ns and TLB lookup takes 20 ns. Each page transfer to/from the disk takes 5000 ns. Assume that the TLB hit ratio is 95%, and among TLB misses, the page fault rate is 10%. Assume that for 20% of those page faults, a dirty page has to be written back to disk before the required page is read in from disk. TLB update time is negligible. The average memory access time in ns (round off to 1 decimal place) is ____.
Explanation
Four disjoint cases: (1) TLB hit (95%): TLB lookup + 1 memory access = 20+100 = 120 ns. (2) TLB miss, no page fault (5%×90% = 4.5%): TLB lookup + page-table memory access + data memory access = 20+100+100 = 220 ns. (3) TLB miss, page fault, no writeback needed (5%×10%×80% = 0.4%): TLB lookup + page-table access + disk read-in + data access = 20+100+5000+100 = 5220 ns. (4) TLB miss, page fault, writeback needed (5%×10%×20% = 0.1%): add one more disk transfer for the writeback = 20+100+5000+5000+100 = 10220 ns. Weighted average = 0.95×120 + 0.045×220 + 0.004×5220 + 0.001×10220 = 114 + 9.9 + 20.88 + 10.22 = 155.0 ns.
Source: GATE CS 2020 (2020)
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