Project ForgeThe instruction pipeline of a RISC processor has stages: IF, ID, OF, PO and WB. The IF, ID, OF and WB stages take 1 clock cycle each for every instruction. Consider a sequence of 100 instructions. In the PO stage, 40 instructions take 3 clock cycles each, 35 instructions take 2 clock cycles each, and the remaining 25 take 1 clock cycle each. There are no data or control hazards. The number of clock cycles required for completion of the sequence is ____.
Explanation
With a variable-duration stage, the pipeline effectively serializes at that stage: total time = (cycles to fill the pipeline up to PO: IF+ID+OF = 3 cycles) + (sum of all instructions' PO durations, since PO can only process one instruction at a time) + (WB for the last instruction: 1 cycle). Sum of PO cycles = 40×3 + 35×2 + 25×1 = 120+70+25 = 215. Total = 3 + 215 + 1 = 219.
Source: GATE CS 2018 (2018)
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