Project ForgeComputer Organization & Architecture
Memory Hierarchy & Floating Point
GATE 2018
Expert
The size of the physical address space of a processor is 2^P bytes. The word length is 2^W bytes. The capacity of cache memory is 2^N bytes. The size of each cache block is 2^M words. For a K-way set-associative cache memory, the length (in number of bits) of the tag field is
- AP − N − log₂K
- P − N + log₂K
- CP − N − M − W − log₂K
- DP − N − M − W + log₂K
Explanation
Block size in bytes = 2^M × 2^W = 2^(M+W), giving offset bits = M+W. Number of cache blocks = 2^N / 2^(M+W) = 2^(N−M−W). Number of sets = (blocks)/K = 2^(N−M−W−log₂K), giving index bits = N−M−W−log₂K. Tag bits = P − index − offset = P − (N−M−W−log₂K) − (M+W) = P − N + log₂K.
Source: GATE CS 2018 (2018)
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