Project ForgeIn a two-level cache system, the access times of L1 and L2 caches are 1 and 8 clock cycles, respectively. The miss penalty from the L2 cache to main memory is 18 clock cycles. The miss rate of L1 cache is twice that of L2. The average memory access time (AMAT) of this cache system is 2 cycles. The miss rates of L1 and L2 respectively are:
- 0.111 and 0.056
- B0.056 and 0.111
- C0.0892 and 0.1784
- D0.1784 and 0.0892
Explanation
AMAT = L1_time + m1×(L2_time + m2×penalty), with m1=2m2: 2 = 1 + 2m2(8+18m2) → 1 = 16m2 + 36m2². Solving 36m2²+16m2−1=0 via the quadratic formula: m2 = (−16+√(256+144))/72 = (−16+20)/72 = 4/72 ≈ 0.0556. Then m1 = 2×0.0556 ≈ 0.111. So L1 miss rate ≈ 0.111 and L2 miss rate ≈ 0.056.
Source: GATE CS 2017 (Session 2) (2017)
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