Project ForgeDigital Logic
Combinational & Sequential Circuits
GATE 2017
Hard
The next state table of a 2-bit saturating up-counter is given below:
Q1 Q0 | Q1+ Q0+ 0 0 | 0 1 0 1 | 1 0 1 0 | 1 1 1 1 | 1 1
The counter is built as a synchronous sequential circuit using T flip-flops. The expressions for T1 and T0 are
- AT1 = Q1Q0, T0 = Q̄1Q̄0
- T1 = Q̄1Q0, T0 = Q̄1+Q̄0
- CT1 = Q1+Q0, T0 = Q̄1+Q̄0
- DT1 = Q̄1Q0, T0 = Q1+Q0
Explanation
T flip-flop input = Q+ XOR Q (T=1 toggles, T=0 holds). T1 = Q1+ ⊕ Q1: for rows 00,01,10,11 this gives 0,1,0,0 — which is exactly Q̄1Q0 (only true when Q1=0,Q0=1). T0 = Q0+ ⊕ Q0: gives 1,1,1,0 — true everywhere except Q1=1,Q0=1, i.e. Q̄1+Q̄0 (De Morgan of NOT(Q1·Q0)).
Source: GATE CS 2017 (Session 2) (2017)
This question is part of a 15-day revision cycle — sign in and Project Forge will bring it back the day before you'd forget it.