Project ForgeConsider a 3 GHz processor with a three-stage pipeline and stage latencies τ1, τ2, and τ3 such that τ1 = 3τ2/4 = 2τ3. If the longest pipeline stage is split into two pipeline stages of equal latency, the new frequency is ____ GHz, ignoring delays in the pipeline registers.
Explanation
Let τ3=x. Then τ1=2x, and τ1=3τ2/4 gives τ2=4τ1/3=8x/3≈2.67x. The current cycle time equals the max stage latency, τ2=8x/3, which must equal 1/3GHz: 8x/3=1/3 → x=1/8 ns-scale unit. So τ1=0.25ns, τ2=0.333ns, τ3=0.125ns. Splitting the longest stage (τ2) into two equal halves gives 0.167ns each. The new max stage latency is now τ1=0.25ns, so the new cycle time is 0.25ns, giving a new frequency of 1/0.25ns = 4GHz.
Source: GATE CS 2016 (Session 2 / Set B) (2016)
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