Project ForgeComputer Organization & Architecture
Pipelining & Instruction Sets
GATE 2016
Medium
The stage delays in a 4-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. The throughput increase of the pipeline is ____ percent.
33.3 %(± 0.5 accepted)
Explanation
Original bottleneck (max stage delay) = 800ps, so old cycle time = 800ps. After restructuring, the new max stage delay = 600ps. Throughput increase = (1/600 − 1/800)/(1/800) × 100% = (800/600 − 1) × 100% ≈ 33.3%.
Source: GATE CS 2016 (Session 1 / Set A) (2016)
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