Project ForgeA positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q̄ output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop, when the flip-flops are connected to a free-running common clock? Assume J=K=1 is toggle mode and J=K=0 is state-holding mode. Both flip-flops have non-zero propagation delays.
- 0110110...
- B0100100...
- C011101110...
- D011001100...
Explanation
Let D_out = D flip-flop's Q, JK_out = JK flip-flop's Q. Initially D_out=1, JK_out=0. On each clock edge: JK gets J=K=D_out (toggle if D_out=1, hold if D_out=0), and D gets input = Q̄ of JK (from BEFORE this edge, due to propagation delay both flip-flops see their pre-edge inputs simultaneously). Tracing: start D=1,JK=0. Edge1: JK toggles (J=K=1)→JK=1; D takes old JK̄=1→D=1. Edge2: JK toggles(D was 1)→JK=0; D takes old JK̄=0→D=0. Edge3: JK holds(D=0)→JK=0; D takes old JK̄=1→D=1. Edge4: JK toggles(D=1)→JK=1; D takes old JK̄=1→D=1. Edge5: JK toggles→JK=0; D takes old JK̄=0→D=0. This settles into the repeating JK output sequence (initial 0, then) 1,0,0,1,1,0,0,1,1,0... i.e. 0,1,1,0,1,1,0... matching 0110110...
Source: GATE CS 2015 (Session 1 / 7th Feb Shift 1) (2015)
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