Question

Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instructions I1, I2, I3, …, I12 is executed in this pipelined processor. Instruction I4 is the only branch instruction and its branch target is I9. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is

Accepted Answer

The correct answer is (B) 165. Clock period = max stage delay + buffer delay = 10+1 = 11 ns. I1-I4 fetch at cycles 1-4. With no prediction, fetching stalls until I4 resolves at the end of its EI stage: I4 goes DI@5, FO@6, EI@7 (completes end of cycle 7). I9 (branch target) then fetches starting cycle 8, and I9-I12 flow through the 5-stage pipeline normally: I9 finishes WO at cycle 12, I10 at 13, I11 at 14, I12 at 15. Total = 15 cycles × 11 ns = 165 ns.

Explanation