Project ForgeComputer Organization & Architecture
Memory Hierarchy & Floating Point
GATE 2012
Hard
Statement for Linked Questions: A computer has a 256 KByte, 4-way set associative, write-back data cache with block size of 32 Bytes. The processor sends 32-bit addresses to the cache controller. Each cache tag directory entry contains, in addition to the address tag, 2 valid bits, 1 modified bit and 1 replacement bit.
The number of bits in the tag field of an address is
- A11
- B14
- 16
- D27
Explanation
Total blocks in cache = 256KB / 32B = 8192 = 2¹³. Number of sets = 8192 / 4-way = 2048 = 2¹¹, needing 11 set-index bits. Block offset needs log₂(32) = 5 bits. Tag bits = 32 − 11 − 5 = 16.
Source: GATE CS 2012 (2012)
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