Project ForgeA 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. IF, ID, OF and WO each take 1 clock cycle. PO takes 1 cycle for ADD/SUB, 3 cycles for MUL, and 6 cycles for DIV. Operand forwarding is used. What is the number of clock cycles needed to execute: I0: MUL R2,R0,R1; I1: DIV R5,R3,R4; I2: ADD R2,R5,R2; I3: SUB R5,R2,R6?
Explanation
Simulating stage-by-stage with the PO stage as a shared single resource (each instruction must wait for it to free up, stalling and backing up earlier stages when necessary): I0 occupies PO for cycles 4-6 (MUL). I1 must wait for PO, entering at cycle 7, occupying it through cycle 12 (DIV, 6 cycles), finishing WO at 13. I2 (needing R5 from I1 and R2 from I0, both available via forwarding well before I2 reaches PO) stalls behind I1 in the pipeline, entering PO at 13, finishing WO at 14. I3 similarly stalls, entering PO at 14, finishing WO at 15.
Source: GATE CS 2010 (2010)
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