Project ForgeWhich of the following are NOT true in a pipelined processor?
I. Bypassing can handle all RAW hazards. II. Register renaming can eliminate all register carried WAR hazards. III. Control hazard penalties can be eliminated by dynamic branch prediction.
- AI and II only
- I and III only
- CII and III only
- DI, II and III
Explanation
Bypassing/forwarding handles MOST but not ALL RAW hazards — the load-use hazard still requires a stall even with forwarding, so I is false (NOT true). Register renaming genuinely CAN eliminate all register-carried WAR (and WAW) hazards by removing false dependencies — II is true. Dynamic branch prediction REDUCES but cannot fully ELIMINATE control hazard penalties, since mispredictions still incur a penalty — III is false (NOT true). So I and III are the NOT-true statements.
Source: GATE CS 2008 (2008)
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