Project ForgeA processor uses 36 bit physical addresses and 32 bit virtual addresses, with a page frame size of 4 Kbytes. Each page table entry is of size 4 bytes. A three level page table is used for virtual-to-physical address translation, where bits 30-31 index the first level page table, bits 21-29 index the second level page table, bits 12-20 index the third level page table, and bits 0-11 are the offset within the page. What is the number of bits required for addressing the next level page table (or page frame) in the page table entry of the FIRST level page table? (Assume each level-2 table occupies exactly its own natural size, 2^11 bytes, and is aligned to that size.)
Explanation
The second-level page table has 2⁹=512 entries of 4 bytes each = 2048 = 2¹¹ bytes, and is naturally aligned to that size. To address a 2¹¹-byte-aligned block within a 36-bit physical address space requires 36-11=25 bits. (By the same logic, the second-level PTE pointing to the equally-sized third-level table also needs 25 bits, while the third-level PTE pointing to an actual 4KB=2¹² data page frame needs 36-12=24 bits — giving the full answer set 25, 25, and 24 across the three levels.)
Source: GATE CS 2008 (2008)
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