Project ForgeComputer Organization & Architecture
Memory Hierarchy & Floating Point
GATE 2008
Hard
(Same cache and array setup as before.) The cache hit ratio for this initialization loop is
- A0%
- B25%
- 50%
- D75%
Explanation
Block size 16 bytes holds exactly 2 doubles (16/8=2). The loop accesses the array strictly sequentially in row-major order, matching memory layout exactly. Each pair of consecutive elements shares one cache block: the first access to a new block is a compulsory MISS, the immediately following second access (same block) is a HIT — a clean alternating MISS,HIT,MISS,HIT,... pattern with no intervening conflicts, giving exactly 50% hit ratio.
Source: GATE CS 2008 (2008)
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