Project ForgeConsider a pipelined processor with four stages IF, ID, EX, WB. IF, ID and WB each take one clock cycle; EX takes 1 clock cycle for ADD/SUB and 3 clock cycles for MUL. Operand forwarding is used. What is the number of clock cycles taken to complete the following sequence of instructions?
ADD R2, R1, R0 (R2 ← R1+R0) MUL R4, R3, R2 (R4 ← R3*R2) SUB R6, R5, R4 (R6 ← R5-R4)
- A7
- 8
- C10
- D14
Explanation
I1(ADD): IF1,ID2,EX3,WB4. I2(MUL) depends on R2 (ready end of I1's EX at cycle3, forwarded): IF2,ID3,EX4-6(3 cycles),WB7. I3(SUB) depends on R4 (ready end of I2's EX at cycle6, forwarded for cycle7): IF3,ID4, stalls until EX7,WB8. Total completion at cycle 8.
Source: GATE CS 2007 (2007)
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