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Computer Organization & Architecture
Memory Hierarchy & Floating Point
GATE 2007
Hard

Consider a 4-way set associative cache consisting of 128 lines with a line size of 64 words. The CPU generates a 20-bit address of a word in main memory. The number of bits in the TAG, LINE and WORD fields of the address are respectively:

  • A9, 6, 5
  • B7, 7, 6
  • C7, 5, 8
  • 9, 5, 6

Explanation

128 lines / 4-way = 32 sets, needing log₂(32)=5 LINE (set index) bits. WORD offset needs log₂(64)=6 bits. TAG = 20-5-6 = 9 bits. So (TAG,LINE,WORD) = (9,5,6).

Source: GATE CS 2007 (2007)

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